In debugging a program executed on an information processing apparatus, such as CPU, from an external debugging apparatus, it is necessary to interconnect the information processing apparatus and the debugging device in some way or other. Such an interconnection method, employing a variety of serial interfaces, provided on the information processing apparatus, is easy to handle and economical, because there is no necessity of newly providing a special interface dedicated to debugging. It is however impossible for a program being debugged to use an interface used for debugging.
The configuration shown for example in FIG. 1 has so far been known as a technique to combat this inconvenience. FIG. 1 depicts a block diagram showing an illustrative configuration for debugging a program being run on a conventional information processing apparatus. The configuration shown includes an information processing apparatus 101, a peripheral device 102, a debugging device 103, and cables 106, 107. It is assumed here that debugging is carried out on the debugging device 103 for a system in which the information processing apparatus 101 and the peripheral device 102 are interconnected over a serial interface 111 and in which data communication 121 pertinent to an application program being run on the information processing apparatus 101 is carried out between the information processing apparatus and the peripheral device.
The information processing apparatus 101 includes memory 130, loaded with a subject of debugging, a CPU (central processing unit) 133, a serial interface 111 and another serial interface 112. The memory 130 has stored therein an application program 131 being debugged and a monitor program 132 for executing commands issued by the debugging device 103. The CPU 133 executes the programs. The serial interface 111 is connected to the memory 130, while being connected over cable 106 to the peripheral device 102. The serial interface 112 is connected to the memory 130, while being connected over cable 107 to the debugging device 103. This debugging device 103 includes software which is an information processing apparatus dedicated to debugging (debugger 135). It is noted that the debugging device 103 and the debugger 135 thereof may be implemented by hardware. A serial interface 113 is connected to the debugger 135, while being connected over cable 107 to the information processing apparatus 101.
The debugging device 103 and the information processing apparatus 101 are interconnected via serial interface 113—cable 107—serial interface 112 to effect data communication 122 pertinent to debugging (control of program execution and status referencing). The operation control and status referencing is carried out by software setting using a monitor program 132 loaded in the information processing apparatus 101. In this case, an additional serial interface 112 needs to be loaded separately on the information processing apparatus 101.
In case it is impossible to provide a serial interface for debugging on the information processing apparatus 101, the configuration shown in FIG. 2 is used. FIG. 2 depicts another conventional illustrative configuration for program debugging operating on an information processing apparatus. In such case, it is necessary to use a mechanism for controlling the CPU 133 in a hardware fashion, such as by an in-circuit emulator (ICE) 104, as a mechanism for controlling the CPU 133, in place of employing the monitor program 132 and the serial interface 112. An interface dedicated to debugging 112a (and a cable 108) need to be provided for interconnecting the ICE 104 and the CPU 133.
In the cases of FIGS. 1 and 2, an interface for debugging needs to be newly provided to the information processing apparatus 101 (the serial interface 112 provided for debugging in FIG. 1 or the interface dedicated to debugging 113 in FIG. 2). As a result, the information processing apparatus 101 needs to be provided with a controller IC, a connector or circuitry for interfacing for debugging with additional costs for the hardware forming the information processing apparatus 101. Moreover, the CPU 133 needs to be provided with connection terminals and functions of an interface dedicated to debugging or additional serial interfacing, with the result that the number of terminals of the chip of the CPU 133 used is correspondingly increased.
Such interface or mechanism is unneeded for the information processing apparatus 101 from the perspective of inherent application and represents redundant costs. It is therefore desirable for a sole interface to be co-used by the application program and the peripheral device 102 on the information processing apparatus 101 and by the debugging device 103.
As a relevant technique, the technique of a single chip micro-computer is disclosed in the JP Patent Kokai Publication No. JP-A-06-324906. This single chip micro-computer has the function of selecting between the single chip micro-computer mode and the debug mode. The single chip micro-computer includes (a) EA/ terminal state storage means for storing the state of the EA/ terminal during the resetting, at the time of selection of the debugging and imparting the stored information to the CPU unit of the chip as an EA/ terminal input, and (b) EA/ terminal connection switching means for switching the EA/ terminal during the debug mode to a debugging terminal of the chip. The debugging information may also be set/ read out from the EA/ terminal of the chip.
As another relevant technique, the technique of a micro-computer, an electronic device and an emulation method are disclosed in the JP patent Kokai Publication No. JP-P2000-276370A. This micro-computer includes a processor for carrying out information processing, an external bus and bus controlling means. The processor executes the commands. An emulation memory and at least another external memory may be connected to the external bus. When the emulation mode is on, the bus control means connects the processor bus to the aforementioned external bus so that the access to an internal memory of the processor is switched to the access to the emulation memory through the aforementioned external bus.
As a further pertinent technique, the technique of a piggy back chip is disclosed in the JP Patent Kokai 4-278646. This piggy back chip includes a functional terminal, equivalent to that of a target micro-computer, on a lateral or lower surface of the package, and a separate terminal for connection to a universal PROM on the upper package surface. The piggy back chip includes a function switching terminal, an inhibit circuit, a switching circuit and a stationary circuit. The function switching terminal is provided on the upper package surface for employing the separate terminal for connection to a universal PROM as a terminal for accessing an enclosed I/O port in the piggy back chip by applying a signal of an effective level. The inhibit circuit inhibits the internal CPU when a signal of an effective level is applied to the function switching terminal. The switching circuit switches the terminal for connection to a universal PROM to the aforementioned terminal for accessing the enclosed I/O port. The stationary circuit sets the terminal to an invalid level in case the function switching terminal is in an opened state.
[Patent Document 1] JP Patent Kokai Publication No. JP-A-06-324906
[Patent Document 2] JP Patent Kokai Publication No. JP-P2000-276370A
[Patent Document 3] JP Patent Kokai Publication No. JP-A-04-278646